Resistive memory is a new class of non-volatile memory, which can retain the stored information when powered off. A resistive memory device normally comprises an array of memory cells, each of which includes at least a resistive memory element and a selection element coupled in series between appropriate electrodes. Upon application of an appropriate voltage or current to the resistive memory element, the electrical resistance of the resistive memory element would change accordingly, thereby switching the stored logic in the respective memory cell.
A resistive memory element can be classified into at least one of several known groups based on its resistively switching mechanism. The resistive memory element of Phase Change Random Access Memory (PCRAM) may comprise a phase change chalcogenide compound, which can switch between a resistive amorphous phase and a conductive crystalline phase. The resistive memory element of Conductive Bridging Random Access Memory (CBRAM) relies on the statistical bridging of metal rich precipitates therein for its switching mechanism. The resistive memory element of CBRAM normally comprises a nominally insulating metal oxide material, which can switch to a lower electrical resistance state as the metal rich precipitates grow and link to form conductive paths upon application of an appropriate voltage. The resistive memory element of Magnetoresistive Random Access Memory (MRAM) typically comprises at least two layers of different ferromagnetic materials with a non-magnetic spacer layer interposed therebetween. When a switching pulse is applied to the memory element of a MRAM device, one of the ferromagnetic layers will switch its magnetic field polarity, thereby changing the element's electrical resistance.
A selection element in a memory cell functions like a switch to direct current through the selected memory element coupled thereto. One common selection element is diode, which can reverse bias a non-selected memory cell. While a selection diode has a simple structure that can minimize the cell size of the resistive memory cell, a memory architecture employing the selection diode normally has a slower random access time. Another commonly used selection element is transistor, which allows for faster selection of memory cells and therefore faster random access time. While a memory device employing the selection transistor is more suitable for the random access type of memories, the more complicated structure of the selection transistor means the size of the memory cell will be larger, which translates to a lower cell density.
FIG. 1 is a perspective view of a conventional resistive memory device comprising a silicon substrate 80, a plurality of memory cells 82 formed therein, a plurality of parallel gate electrodes 84 connecting the cells 82 in a first direction, a plurality of parallel source lines 86 connecting the cells 82 in the first direction, and a plurality of bit lines 88 connecting the cells 82 in a second direction substantially perpendicular to the first direction. Each of the memory cells 82 includes a respective one of a plurality of resistive memory elements 90 and a respective one of a plurality of conventional selection transistors 92 connected in series by way of a respective one of a plurality of contacts 94. The channels of the selection transistors 92 beneath the gate electrodes 84 have a length of 1 F and a width of 1 F, where F denotes the minimum feature size or one half the minimum feature pitch normally associated with a particular lithography process. In memory applications where memory cells are arranged in dense and repetitive patterns, photolithography is more constrained by the pitch of the feature pattern rather than the feature size itself. This is because the feature size can be modulated by photo lithography process conditions, such as exposure and resist development, but shrinkage of the feature pitch would require shorter wavelength light source and/or significant improvement in optics. In reality, the scaling of the device size in a dense array, such as that in memory applications, is limited by the minimum feature pitch of 2 F. Moreover, it is normally assumed that the minimum feature size is half of the corresponding minimum pitch. The illustrated conventional resistive memory device in FIG. 1 has cell dimensions of 4 F and 2 F in the directions of bit lines 88 and source lines 86, respectively, resulting in a cell size of 8 F2. As would be understood by one of ordinary skill in the art, the minimum pitch between two repetitive features on a same mask layer is 2 F. Accordingly, the minimum size of a memory cell would be 4 F2 when arranged in a square array using conventional lithography.
To be cost competitive, a small memory cell size is desired in order to increase device density. One way to achieve this is to simply shrink the feature size, F. However, several difficulties can arise when scaling the size of the conventional transistors 92 illustrated in FIG. 1, particularly its channel length, to sizes of a few tens of nanometers. As the channel length is reduced, there is a propensity for the formation of parasitic conduction paths between source and drain, thereby causing punch through current leakages. Another obstacle encountered in shrinking the conventional transistors 92 is reduced current drivability caused by the reduced width of the current carrying channel. This is a significant issue for resistive memory devices, which require higher current to switch their memory state.
Another way to reduce the memory cell size is to use a different architecture that would permit the memory cell size to scale down to the minimum size of 4 F2 while increasing the channel width and length to mitigate the above mentioned problems associated with shrinking feature size. With the source, drain, and channel of the selection transistor lie on a same plane, the conventional resistive memory cell size as illustrated in FIG. 1 is limited to 8 F2. Moreover, the corresponding channel width and length of the conventional selection transistor would both be 1 F.